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preliminary clock generator for intel ? grantsdale chipset cy28412 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07612 rev. *c revised december 21, 2004 features ? supports intel ? p4 and prescott cpu ? selectable cpu frequencies ? differential cpu clock pairs ? 100-mhz differential src clocks ? 96-mhz differential dot clock ? 48-mhz usb clocks ? 33-mhz pci clock ? low-voltage frequency select input ?i 2 c support with read back capabilities ? ideal lexmark spread spectrum profile for maximum electromagnetic interference (emi) reduction ? 3.3v power supply ? 56-pin ssop package cpu src pci ref dot96 usb_48 x2 / x3 x7 / x8 x 8 x 2 x 1 x 1 block diagram pin configuration pci0 pci1 gnd_pci pci2 pci3 pci4 pci5 gnd_pci vdd_pci test_sel/pcif0 itp_en/pcif1 vdd_48 usb48/fs_b gnd_48 dot96t dot96c vtt_pwrgd#/pd srct0 srcc0 srct1 stcc1 vdd_src gnd_src srct2 vdd_ref ref0/fs_c srcc3 srct5 cpuc2_itp/srcc6 vdd_src cput2_itp/srct6 gnd_a vdd_a iref cput1 cpuc1 vdd_cpu cput0 cpuc0 gnd_cpu sdata x2 gnd_ref x1 ref1/fs_a srcc5 srcc2 satat satac gnd_src srct4 srct3 vdd_src 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 32 31 30 29 vdd_ref xtal pll ref freq xout xin osc sclk pll1 i 2 c logic vdd_48 mhz sdata vdd_pci divider network vdd_cpu fs_[c:a] ref[1:0] vtt_pwrgd# iref pci[0:5] pll2 cput[0:1], cpuc[0:1], vdd_src srct[0:6], srcc[0:6], usb_48 cpu_stp# pci_stp# vdd_pci srcc4 sclk cy28412 56 ssop dot96t dot96c vdd_pcif pcif[0:1] cpu(t/c)2_itp] pd sata[t/c]
preliminary cy28412 document #: 38-07612 rev. *c page 2 of 17 pin definitions pin no. name type description 47,46,44,43 cput/c o, dif differential cpu clock outputs . 39,38 cput2_itp/srct6, cpuc2_itp/srcc6 o, dif selectable differential cpu or src clock output . itp_en = 0 @ vtt_pwrg d# assertion = src6 itp_en = 1 @ vtt_pwrg d# assertion = cpu2 16,17 dot96t, dot96c o, dif fixed 96-mhz clock output . 55, 54 ref0/fs_c, ref1/fs_a i/o 14.318-mhz reference cl ock/3.3v-tolerant input fo r cpu frequency selection. input is latched upon assertion (low) of vtt_pwrgd#/pd refer to dc electrical specifications t able for vil_fs and vih_fs specifications. 14 usb48/fs_b i/o fixed 48-mhz usb clock output/3.3v -tolerant input for cpu frequency selection . input is latched upon assertion (low) of vtt_pwrgd#/pd refer to dc electrical specifications t able for vil_fs and vih_fs specifications. 42 iref i a precision resistor is attached to this pin, which is connected to the internal current reference . 1,2,5,6,7,8 pci[0:5] o, se 33-mhz clocks . 11 test_sel/pcif0 i/o free-running 33-mhz cloc ks/ 3.3v-tolerant input for selecting test mode . input is latched upon assertion (low) of vtt_pwrgd#/pd 1 = all outputs are three-stated for test 0 = all outputs normal operation **this input has an internal pull-down resistor. 12 itp_en/pcif1 i/o, se free-running 33-mhz clock/cpu2 select (sampled on the vtt_pwrgd# assertion) . 1 = cpu2_itp, 0 = src6 49 sclk i smbus-compatible sclock . 50 sdata i/o smbus-compatible sdata . 27,28 satat, satac o, dif differential serial reference clock . recommended output for sata. 19,20,21,22, 25,26,30,31, 32,33,35,36 srct/c[0:5] o, dif differential serial reference clocks . 13 vdd_48 pwr 3.3v power supply for outputs. 45 vdd_cpu pwr 3.3v power supply for outputs. 3,10 vdd_pci pwr 3.3v power supply for outputs. 56 vdd_ref pwr 3.3v power supply for outputs. 23,29,37 vdd_src pwr 3.3v power supply for outputs. 40 vdd_a pwr 3.3v power supply for pll. 15 gnd_48 gnd ground for outputs. 48 gnd_cpu gnd ground for outputs. 4,9 gnd_pci gnd ground for outputs. 53 gnd_ref gnd ground for outputs. 24,34 gnd_src gnd ground for outputs. 41 gnd_a gnd ground for pll. 18 vtt_pwrgd#/pd i, pu 3.3v lvttl input is a level sensitive strobe used to latch the ref0/fsc, ref1/fsa, usb48/fsb, test_sel/p cif0 and itp_en/pcif1 inputs . after vtt_pwrgd# (active low) assertion, th is pin becomes a realtime input for asserting power-down (active high). 52 x1 i 14.318-mhz crystal input . 51 x2 o, se 14.318-mhz crystal output .
preliminary cy28412 document #: 38-07612 rev. *c page 3 of 17 frequency select pins (fs_a, fs_b and fs_c) host clock frequency selection is achieved by applying the appropriate logic levels to fs_a, fs_b, fs_c inputs prior to vtt_pwrgd# assertion (as seen by the clock synthesizer). upon vtt_pwrgd# being sampled low by the clock chip (indicating processor vtt voltage is stable), the clock chip samples the fs_a, fs_b and fs_c input values. for all logic levels of fs_a, fs_b and fs_c vtt_pwrgd# employs a one-shot functionality in that once a valid low on vtt_pwrgd# has been sampled, all further vtt_pwrgd#, fs_a, fs_b and fs_c transitions will be ignored, except in test mode. serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. the registers associated with the serial data interface initial- izes to their default setting upon power-up, and therefore use of this interface is optional. clock device register changes are normally made upon system initializ ation, if any are required. the interface cannot be used during system operation for pow- er management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. for block write/read operation, the bytes must be accessed in se- quential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the sys- tem controller can access individually indexed bytes. the off- set of the indexed byte is encoded in the command code, as described in ta ble 2 . the block write and block read protocol is outlined in table 3 while table 4 outlines the correspondi ng byte write and byte read protocol. the slave receiver address is 11010010 (d2h). table 1. frequency select table (fs_a, fs_b, fs_c) fs_c fs_b fs_a cpu src pcif/pci ref0 dot96 usb 1 0 1 100 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 0 1 133 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 1 1 166 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 1 0 200 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 0 0 0 266 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 1 0 0 333 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 1 1 0 400 mhz 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz 1 1 1 reserved 100 mhz 33 mhz 14.318 mhz 96 mhz 48 mhz table 2. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operation. for block read or block write operations, these bits should be '0000000 ' table 3. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write = 0 9 write = 0 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bits '00000000' stands for block operation 11:18 command code ? 8 bits '00000000' stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 1 ? 8 bits 28 read = 1 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 2 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge from master
preliminary cy28412 document #: 38-07612 rev. *c page 4 of 17 control registers .... ...................... 39:46 data byte from slave ? 8 bits .... data byte (n ? 1) ? 8 bits 47 acknowledge from master .... acknowledge from slave 48:55 data byte from slave ? 8 bits .... data byte n ? 8 bits 56 acknowledge from master .... acknowledge from slave .... data byte n from slave ? 8 bits .... stop .... acknowledge from master .... stop table 4. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1start 1start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write = 0 9 write = 0 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed 11:18 command code ? 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 data byte from master ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29 stop 28 read = 1 29 acknowledge from slave 30:37 data byte from slave ? 8 bits 38 acknowledge from master 39 stop table 3. block read and block write protocol (continued) block write protocol block read protocol bit description bit description byte 0:control register 0 bit @pup name description 7 1 cput2_itp/srct6 cpuc2_itp/srcc6 cpu[t/c]2_itp/src[t/ c]6 output enable 0 = disable (hi-z), 1 = enable 6 1 src[t/c]5 src[t/c]5 output enable 0 = disable (hi-z), 1 = enable 5 1 src[t/c]4 src[t/c]4 output enable 0 = disable (hi-z), 1 = enable 4 1 src[t/c]3 src[t/c]3 output enable 0 = disable (hi-z), 1 = enable 3 1 satat/c] sata[t/c] output enable 0 = disable (hi-z), 1 = enable 2 1 src[t/c]2 src[t/c]2 output enable 0 = disable (hi-z), 1 = enable 1 1 src[t/c]1 src[t/c]1 output enable 0 = disable (hi-z), 1 = enable 0 1 src[t/c]0 src[t/c]0 output enable 0 = disable (hi-z), 1 = enable
preliminary cy28412 document #: 38-07612 rev. *c page 5 of 17 byte 1: control register 1 bit @pup name description 7 1 cput/c srct/c pcif pci center spread enable 0 = 0.25% center spread, 1 = ?0.5% down spread 6 1 dot_96t/c dot_96 mhz output enable 0 = disable (hi-z), 1 = enabled 5 1 usb_48 usb_48 mhz output enable 0 = disabled, 1 = enabled 4 1 ref0 ref0 output enable 0 = disabled, 1 = enabled 3 1 ref1 ref1 output enable 0 = disabled, 1 = enabled 2 1 cpu[t/c]1 cpu[t/c]1 output enable 0 = disable (hi-z), 1 = enabled 1 1 cpu[t/c]0 cpu[t/c]0 output enable 0 = disable (hi-z), 1 = enabled 0 0 cput/c srct/c pcif pci spread spectrum enable 0 = spread off, 1 = spread on byte 2: control register 2 bit @pup name description 7 1 pci5 pci5 output enable 0 = disabled, 1 = enabled 6 1 pci4 pci4 output enable 0 = disabled, 1 = enabled 5 1 pci3 pci3 output enable 0 = disabled, 1 = enabled 4 1 pci2 pci2 output enable 0 = disabled, 1 = enabled 3 1 pci1 pci1 output enable 0 = disabled, 1 = enabled 2 1 pci0 pci0 output enable 0 = disabled, 1 = enabled 1 1 pcif1 pcif1 output enable 0 = disabled, 1 = enabled 0 1 pcif0 pcif0 output enable 0 = disabled, 1 = enabled byte 3: control register 3 bit @pup name description 7 0 cput2_itp/srct6 cpuc2_itp/srcc6 allow control of src[t/c]6 wit h assertion of sw pci_stp# 0 = free-running, 1 = stopped with sw pci_stp# 6 0 src[t/c]5 allow control of src[t/ c]5with assertion of sw pci_stp# 0 = free-running, 1 = stopped with sw pci_stp# 5 0 src[t/c]4 allow control of src[t/ c]4 with assertion of sw pci_stp# 0 = free-running, 1 = stopped with sw pci_stp# 4 0 src[t/c]3 allow control of src[t/ c]3with assertion of sw pci_stp# 0 = free-running, 1 = stopped with sw pci_stp# 3 0 sata[t/c] allow control of sata[t /c] with assertion of sw pci_stp# 0 = free-running, 1 = stopped with sw pci_stp#
preliminary cy28412 document #: 38-07612 rev. *c page 6 of 17 2 0 src2 allow control of src[t/c] 2 with assertion of sw pci_stp# 0 = free-running, 1 = stopped with sw pci_stp# 1 0 src1 allow control of src[t/c] 1 with assertion of sw pci_stp# 0 = free-running, 1 = stopped with sw pci_stp# 0 0 src0 allow control of src[t/c] 0 with assertion of sw pci_stp# 0 = free-running, 1 = stopped with sw pci_stp# byte 4: control register 4 bit @pup name description 7 0 reserved reserved, set = 0 6 0 dot96[t/c] dot_pwrdwn drive mode 0 = driven in pwrdwn, 1 = hi-z 5 0 pcif1 allow control of pcif2 with assertion of sw pci_stp# 0 = free-running, 1 = stopped with sw pci_stp# 4 0 pcif0 allow control of pcif1 with assertion of sw pci_stp# 0 = free-running, 1 = stopped with sw pci_stp# 3 0 reserved reserved, set = 0 2 1 reserved reserved, set = 1 1 1 reserved reserved, set = 1 0 1 reserved reserved, set = 1 byte 5: control register 5 bit @pup name description 7 0 src[t/c][6:0],sat a[t/c] src[t/c], sata [t/c]stop drive mode 0 = driven when sw pci_stp# asse rted,1 = hi-z when pci_stp# asserted 6 0 reserved reserved, set = 0 5 0 reserved reserved, set = 0 4 0 reserved reserved, set = 0 3 0 src[t/c][6:0],sata[ t/c] src[t/c], sata[t/c] pwrdwn drive mode 0 = driven when pd asserted,1 = hi-z when pd asserted 2 0 cpu[t/c]2 cpu[t/c]2 pwrdwn drive mode 0 = driven when pd asserted,1 = hi-z when pd asserted 1 0 cpu[t/c]1 cpu[t/c]1 pwrdwn drive mode 0 = driven when pd asserted,1 = hi-z when pd asserted 0 0 cpu[t/c]0 cpu[t/c]0 pwrdwn drive mode 0 = driven when pd asserted,1 = hi-z when pd asserted byte 3: control register 3 (continued) bit @pup name description
preliminary cy28412 document #: 38-07612 rev. *c page 7 of 17 crystal recommendations the cy28412 requires a parallel resonance crystal . substituting a series resonance crystal will cause the cy28412 to operate at the wrong frequency and violate the ppm specification. for most ap plications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. crystal loading crystal loading plays a critical ro le in achieving low ppm perfor- mance. to realize low ppm perf ormance, the total capacitance the crystal will see must be considered to calculate the appro- priate capacitive loading (cl). the following diagram shows a typical crystal configuration using the two trim capacitors. an important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. it?s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. this is not true. byte 6: control register 6 bit @pup name description 7 0 reserved reserved, set = 0 6 0 test clock mode entry control 1 = hi-z mode, 0 = normal operation 5 1 ref1 ref1 output drive strength 0 = low, 1 = high 4 1 ref0 ref0 output drive strength 0 = low, 1 = high 3 1 pcif, src, pci sw pci_stp# function 0=sw pci_stp assert, 1= sw pci_stp deassert when this bit is set to 0, all stop pable pci, pcif and src outputs will be stopped in a synchronous manner with no short pulses. when this bit is set to 1, all sto pped pci, pcif and src outputs will resume in a synchronous manner with no short pulses. 2 externally selected cput/c fs_c. reflects the value of the fs_c pin sampled on power up 0 = fs_c was low during vtt_pwrgd# assertion 1 externally selected cput/c fs_b. reflects the value of the fs_b pin sampled on power up 0 = fs_b was low during vtt_pwrgd# assertion 0 externally selected cput/c fs_a. reflects the value of the fs_a pin sampled on power up 0 = fs_a was low during vtt_pwrgd# assertion byte 7: vendor id bit @pup name description 7 0 revision code bit 3 revision code bit 3 6 0 revision code bit 2 revision code bit 2 5 1 revision code bit 1 revision code bit 1 4 0 revision code bit 0 revision code bit 0 3 1 vendor id bit 3 vendor id bit 3 2 0 vendor id bit 2 vendor id bit 2 1 0 vendor id bit 1 vendor id bit 1 0 0 vendor id bit 0 vendor id bit 0 table 5. crystal recommendations frequency (fund) cut loading load cap drive (max.) shunt cap (max.) motional (max.) tolerance (max.) stability (max.) aging (max.) 14.31818 mhz at parallel 20 pf 0.1 mw 5 pf 0.016 pf 50 ppm 50 ppm 5 ppm
preliminary cy28412 document #: 38-07612 rev. *c page 8 of 17 calculating load capacitors in addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal load ing. as mentioned previously, the capacitance on each side of the crystal is in series with the crystal. this means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitive loading on both sides. as mentioned previously, the capacitance on each side of the crystal is in series with the cr ystal. this mean the total capac- itance on each side of the crystal must be 2 times the specified load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, trim capacitors (ce1,ce2) should be calculated to provide equal capacitance loading on both sides. use the following formulas to calculate the trim capacitor values for ce1 and ce2. cl ........................................... .........crystal load capacitance cle ............. .............. .............. actual loading seen by crystal using standard value trim capacitors ce ..................................................... external trim capacitors cs ........................................ ......stray capaci tance (terraced) ci .......................................................... internal capacitance (lead frame, bond wires etc.) pd (power-down) clarification the vtt_pwrgd# /pd pin is a dual function pin. during initial power-up, the pin functions as vtt_pwrgd#. once vtt_pwrgd# has been sampled low by the clock chip, the pin assumes pd functionality. the pd pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the device. this signal is synchronized internal to the device prior to powering down the clock synthe- sizer. pd is also an asynchronous input for powering up the system. when pd is asserted hi gh, all clocks are driven to a low value and held prior to turning off the vcos and the crystal oscillator. pd (power-down) ? assertion when pd is sampled high by two consecutive rising edges of cpuc, all single-ended outputs will be held low on their next high to low transiti on and differential clocks must be held high or hi-z (depending on the state of the control register drive mode bit) on the next diff clock# high to low transition. when the smbus pd drive mode bit corresponding to the differential figure 1. crystal capacitive clarification xtal ce2 ce1 cs1 cs2 x1 x2 ci1 ci2 clock chip trace 2.8pf trim 33pf pin 3 to 6p figure 2. crystal loading example load capacitance (each side) total capacitance (as seen by the crystal) ce = 2 * cl ? (cs + ci) ce1 + cs1 + ci1 1 + ce2 + cs2 + ci2 1 ( ) 1 = cle
preliminary cy28412 document #: 38-07612 rev. *c page 9 of 17 (cpu, src, and dot) clock output of interest is programmed to ?0?, the clock output must be held with ?diff clock? pin driven high at 2 x iref, and ?diff clock#? tristate. if the control register pd drive mode bit corresponding to the output of interest is programmed to ?1?, then both the ?diff clock? and the ?diff clock#? are hi-z. note the example below shows cput = 133 mhz and pd drive mode = ?1? for all differential outputs. this diagram and description is applicable to valid cpu frequencies 100,133,166,200,266, 333, and 400 mhz. in the event that pd mode is desired as the initial power-on state, pd must be asserted high in less than 10 s after asserting vtt_pwrgd#. pd deassertion the power-up latency is less than 1.8 ms. this is the time from the deassertion of the pd pin or the ramping of the power supply until the time that stab le clocks are output from the clock chip. all differential outputs stopped in a tristate condition resulting from power down must be driven high in less than 300 s of pd deassertion to a voltage greater than 200 mv. after the clock chip?s internal pll is powered up and locked, all outputs are ena bled within a few clock cycles of each other. below is an example showing the relationship of clocks coming up. figure 3. power-down assertion timing waveform pd usb, 48mhz dot96t dot96c srct 100mhz srcc 100mhz cput, 133mhz pci, 33 mhz ref cpuc, 133mhz figure 4. power-down deassertion timing waveform dot96c pd cpuc, 133mhz cput, 133mhz srcc 100mhz usb, 48mhz dot96t srct 100mhz tstable <1.8ms pci, 33mhz ref tdrive_pwrdn# <300 s, >200mv
preliminary cy28412 document #: 38-07612 rev. *c page 10 of 17 fs_a, fs_b,fs_c vtt_pwrgd# pwrgd_vrm vdd clock gen clock state clock outputs clock vco 0.2-0.3ms delay state 0 state 2 state 3 wait for vtt_pwrgd# sample sels off off on on state 1 device is not affected, vtt_pwrgd# is ignored figure 5. vtt_pwrgd# timing diagram vtt_pwrgd# = low delay >0.25ms s1 power off s0 vdd_a = 2.0v sample inputs straps s2 normal operation wait for <1.8ms enable outputs s3 vtt_pwrgd# = toggle vdd_a = off figure 6. clock generator power-up/run state diagram
preliminary cy28412 document #: 38-07612 rev. *c page 11 of 17 absolute maximum conditions parameter description condition min. max. unit v dd core supply voltage ?0.5 4.6 v v dd_a analog supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd + 0.5 vdc t s temperature, storage non-functional ?65 150 c t a temperature, operating ambient functional 0 70 c t j temperature, junction functional ? 150 c ? jc dissipation, junction to case mil-spec 883e method 1012.1 ? 31.89 c/w ? ja dissipation, junction to ambient jedec (jesd 51) ? 48.29 c/w esd hbm esd protection (human body model) mil-std-883, method 3015 2000 ? v ul-94 flammability rating at 1/8 in. v?0 msl moisture sensitivity level 1 multiple supplies: the voltage on any input or i/o pin cannot ex ceed the power pin during power- up. power supply sequencing is not required. dc electrical specifications parameter description condition min. max. unit vdd_a , vdd_ref, vdd_pci, vdd_3v66, vdd_48, vdd_cpu 3.3v operating voltage 3.3 5% 3.135 3.465 v v ili2c input low voltage sdata, sclk ? 1.0 v v ihi2c input high voltage sdata, sclk 2.2 ? v v il_fs fs_(a,b,c) input low voltage v ss ? 0.3 0.35 v v ih_fs fs_(a,b,c) input high voltage 0.7 v dd + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v ih input high voltage 2.0 v dd + 0.5 v i il input low leakage current except internal pull-up resistors, 0 < v in < v dd ?5 a i ih input high leakage current except internal pull-down resistors, 0 < v in < v dd 5 a v ol output low voltage i ol = 1 ma ? 0.4 v v oh output high voltage i oh = ?1 ma 2.4 ? v i oz high-impedance output current ?10 10 a c in input pin capacitance 2 5 pf c out output pin capacitance 3 6 pf l in pin inductance ?7nh v xih xin high voltage 0.7v dd v dd v v xil xin low voltage 00.3v dd v i dd3.3v dynamic supply current at max load and freq per figure 8 ? 500 ma i pd3.3v power-down supply current pd asserted, outputs driven ? 75 ma i pd3.3v power-down supply current pd asserted, outputs hi-z ? 2 ma
preliminary cy28412 document #: 38-07612 rev. *c page 12 of 17 ac electrical specifications parameter description condition min. max. unit crystal t dc xin duty cycle the device will operate reliably with input duty cycles up to 30/70 but the ref clock duty cycle will not be within specification 47.5 52.5 % t period xin period when xin is driven from an external clock source 69.841 71.0 ns t r / t f xin rise and fall times measured between 0.3v dd and 0.7v dd ? 10.0 ns t ccj xin cycle to cycle jitter as an average over 1- s duration ? 500 ps l acc long-term accuracy over 150 ms ? 300 ppm cpu at 0.7v t dc cput and cpuc duty cycle mea sured at crossing point v ox 45 55 % t period 100 mhz cput and cpuc period measured at crossing point v ox 9.9970 10.003 ns t period 133 mhz cput and cpuc period measured at crossing point v ox 7.4978 7.5023 ns t period 166 mhz cput and cpuc period measured at crossing point v ox 5.9982 6.0018 ns t period 200 mhz cput and cpuc period measured at crossing point v ox 4.9985 5.0015 ns t period 266 mhz cput and cpuc period measured at crossing point v ox 3.7489 3.7511 ns t period 333 mhz cput and cpuc period measured at crossing point v ox 2.9991 3.0009 ns t period 400 mhz cput and cpuc period measured at crossing point v ox 2.4993 2.5008 ns t periodss 100 mhz cput and cpuc period, ssc measured at crossing point v ox 9.9970 10.0533 ns t periodss 133 mhz cput and cpuc period, ssc measured at crossing point v ox 7.4978 7.5400 ns t periodss 166 mhz cput and cpuc period, ssc measured at crossing point v ox 5.9982 6.0320 ns t periodss 200 mhz cput and cpuc period, ssc measured at crossing point v ox 4.9985 5.0266 ns t periodss 266 mhz cput and cpuc period, ssc measured at crossing point v ox 3.7489 3.7700 ns t periodss 333 mhz cput and cpuc period, ssc measured at crossing point v ox 2.9991 3.0160 ns t periodss 400 mhz cput and cpuc period, ssc measured at crossing point v ox 2.4993 2.5133 ns t skew any cput/c to cput/c clock skew, ssc measured at crossing point v ox ? 100 ps t ccj cput/c cycle to cycle jitter measured at crossing point v ox ?85ps t ccj2 cpu2_itp cycle to cycle jitter measured at crossing point v ox ? 125 ps t skew2 cpu2_itp to cpu0 clock skew measured at crossing point v ox ? 150 ps t r / t f cput and cpuc rise and fall times measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f )? 20 % ? t r rise time variation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math averages figure 8 660 850 mv v low voltage low math averages figure 8 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 8 . measure se ? 0.2 v src t dc srct and srcc duty cycle mea sured at crossing point v ox 45 55 % t period 100 mhz srct and srcc period measured at crossing point v ox 9.9970 10.003 ns t periodss 100 mhz srct and srcc period, ssc measured at crossing point v ox 9.9970 10.0533 ns
preliminary cy28412 document #: 38-07612 rev. *c page 13 of 17 t ccj srct/c cycle to cycle jitter measured at crossing point v ox ? 125 ps l acc srct/c long term accuracy measured at crossing point v ox ? 300 ppm t r / t f srct and srcc rise and fall times measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f )? 20 % ? t r rise time variation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math averages figure 8 660 850 mv v low voltage low math averages figure 8 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 8. measure se ? 0.2 v t skew any srct/c to srct/c clock skew measured at crossing point v ox ? 250 ps pci/pcif t dc pci duty cycle measurement at 1.5v 45 55 % t period spread disabled pcif/pci period me asurement at 1.5v 29.9910 30.0090 ns t period spread enabled pcif/pci period me asurement at 1.5v 29.9910 30.1598 ns t high pcif and pci high time measurement at 2.4v 12.0 ? ns t low pcif and pci low time measurement at 0.4v 12.0 ? ns t r / t f pcif and pci edge rate measured between 0.8v and 2.0v 0.5 2.0 v/ns t skew any pci clock to any pci clock skew measurement at 1.5v ? 500 ps t ccj pcif and pci cycle to cycle jitter measurement at 1.5v ? 500 ps dot t dc dot96t and dot96c duty cycle measured at crossing point v ox 45 55 % t period dot96t and dot96c period measured at crossing point v ox 10.4135 10.4198 ns t ccj dot96t/c cycle to cycle jitter m easured at crossing point v ox ? 250 ps l acc dot96t/c long term accuracy measured at crossing point v ox ? 300 ppm t r / t f dot96t and dot96c rise and fall times measured from v ol = 0.175 to v oh = 0.525v 175 700 ps t rfm rise/fall matching determined as a fraction of 2*(t r ? t f )/(t r + t f )? 20 % ? t r rise time variation ? 125 ps ? t f fall time variation ? 125 ps v high voltage high math averages figure 8 660 850 mv v low voltage low math averages figure 8 ?150 ? mv v ox crossing point voltage at 0.7v swing 250 550 mv v ovs maximum overshoot voltage ? v high + 0.3 v v uds minimum undershoot voltage ?0.3 ? v v rb ring back voltage see figure 8. measure se ? 0.2 v usb t dc duty cycle measurement at 1.5v 45 55 % t period period measurement at 1.5v 20.8271 20.8396 ns t high usb high time measurement at 2.4v 8.094 10.036 ns t low usb low time measurement at 0.4v 7.694 9.836 ns ac electrical specifications (continued) parameter description condition min. max. unit
preliminary cy28412 document #: 38-07612 rev. *c page 14 of 17 test and measurement set-up for pci single-ended signals and reference the following diagram shows the test load configurations for the single-ended pci, usb, and ref output signals. t r / t f usb edge rate measured between 0.8v and 2.0v 1.0 2.0 v/ns t ccj usb cycle to cycle jitter measurement at 1.5v ? 350 ps ref t dc ref duty cycle measurement at 1.5v 45 55 % t period ref period measurement at 1.5v 69.8203 69.8622 ns t r / t f ref edge rate measured betw een 0.8v and 2.0v 0.5 2.0 v/ns t ccj ref cycle to cycle jitter me asurement at 1.5v ? 1000 ps enable/disable and setup t stable clock stabilization from power-up ? 1.8 ms t ss stopclock set-up time 10.0 ? ns t sh stopclock hold time 0 ? ns ac electrical specifications (continued) parameter description condition min. max. unit figure 7. single-ended load configuration pci/ usb ref 12? measurement point 4pf 12? measurement point 4pf 12? measurement point 4pf 12? measurement point 4pf 12? measurement point 4pf 60? 60? 60? 60? 60?
preliminary cy28412 document #: 38-07612 rev. *c page 15 of 17 for differential cpu, src and dot96 output signals the following diagram shows the test load configuration for the differential cpu and src outputs. ordering information part number package type product flow standard CY28412OC 56-pin ssop commercial, 0 to 70c CY28412OCt 56-pin ssop ? tape and reel commercial, 0 to 70c lead-free cy28412oxc 56-pin ssop commercial, 0 to 70c cy28412oxct 56-pin ssop ? tape and reel commercial, 0 to 70c cput cpuc 33? 33? 49.9? 49.9? measurement point 2pf 475? ir e f measurement point 2pf srct srcc 100? d ifferential dot96t dot96c figure 8. 0.7v single-ended load configuration 2.4v 0.4v 3.3v 0v t r t f 1.5v 3.3v si g nals t dc - - figure 9. single-ended output si gnals (for ac parameters measurement)
preliminary cy28412 document #: 38-07612 rev. *c page 16 of 17 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. purchase of i 2 c components from cypress or one of its sublicensed as sociated companies conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. intel and pentium are registered trademar ks of intel corporation. all pr oduct and company names mentione d in this document are the trademarks of their respective holders. package drawing and dimensions 56-lead shrunk small outline package o56 51-85062-*c
preliminary cy28412 document #: 38-07612 rev. *c page 17 of 17 document history page document title: cy28412 clock generator for intel ? grantsdale chipset document number: 38-07612 rev. ecn no. issue date orig. of change description of change ** 131327 12/08/03 rgl new data sheet *a 208217 see ecn rgl corrected theta ja/jc values added t ccj2 specs in the ac electrical specs table added t skew2 specs in the ac electrical specs table fixed figure 7 0.7v single-ended load config changed max pd supply current from 70 to 75 ma in the ac electrical specs table *b 249075 see ecn rgl fixed the loading diagram changed the revision id changed the power supply current for hi-z to 2 ma *c 305733 see ecn rgl changed single-ended outputs from rise /fall times to edge rate changed byte 1 bit 7 from reserved to enable center spread

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